TD — Sequential Logic


D Flip-Flop with Enable

We would like to construct a D flip-flop with a synchronous and active high reset and an additional input en:

  • When en is high, the flip-flop works as usual
  • When en is low, the flip-flop is frozen such that the output Q maintains its value even after a rising clock edge

Question 1: Using paper and pencil, draw a schematics implementing the above specification, using a standard D flip-flop and additional logic gates.

In order to verify if your design is correct, switch to the terminal and go to root folder of the archive. Type

cd dff
logisim dff-impl.circ &

to open the template circuit. Once you are done with your design, execute the testbench by typing


In the waveform viewer, compare the two waveforms of Q.

Rising Edge Detector

The clock, which is defined globally for the whole circuit, is the only signal that may be used as synchonising input of flip-flops. Sometimes however, we are interested in knowing wether a signal has changed from 0 to 1 (or from 1 to zero) from one clock cycle to the next. Consider the following timing diagram:

It shows the behavior of a rising edge detector. Whenever the input D changes from 0 to 1, it outputs a pulse of one clock cycle at the output top.

Question 1: Propose an implementation of the rising edge detector using one or several flip-flops and basic logic gates. How can you assure that the output pulse lasts exactly one clock cycle even if the input D is not synchronous to the clock signal?

You can test your design using the testbench in the subdirectory edge:

cd edge 
logisim edgedetect-impl.circ &

Question 2: Modify your design in order to detect

  1. A falling edge (from 1 to 0)
  2. Both rising and falling edges

Serial to Parallel Conversion

Serial communications are used in many applications. You might have heard of the USB standard, which stands for Universal Serial Bus. Other (simpler) protocols include SPI or I2C. The advantage of transmitting data serially (i.e. one bit at a time) is the small number of required signals, which reduces the number of input and output pins of integrated circuits and the hardware costs for transmission cables. However, since in a computer, data is stored as words, for example in chunks of 8 bits, we need to somehow reconstruct the (parallel) representation from the serial data received over time.

Consider the following specification:

  • We are receiving in a synchronous manner, a sequence of bits on the input \(S_{in}\) (serial in)
  • We would like to transform the received data to words of 4 bit and present them at the output \(P_{out}\) (parallel out)
  • The bits are received in the order of their indices, i.e. the first bit received shall correspond to the least significant bit of the output
  • An additional output \(valid\) shall indicate whenever the output is valid (i.e. whenever a full sequence of four bits has been received)

Question 1: Implement the serial-to-parallel converter using flip-flops and basic logic gates. You can leave out the generation of the \(valid\) signal and add it later.

Once you are satisfied with your design, implement it in logism and test it using the provided testbench:

cd ser2par
logisim ser2par-impl.circ &

Below is a timing diagram showing the transmission of three consecutive messages: 1001, 0101, and 1100.


In this exercise we will play with counters. The basic structure of a counter has been presented during the lecture:

8 bit modulo counter with asynchronous reset

The above figure shows an 8 bit counter (with asynchronous negative reset), which counts modulo 256. It consists basically of a register and an adder doing the arithmetics. Starting from this simple structure, we are going to add some more interesting functionality.

You can find the logisim environment for this exercise in the subdirectory count. Execute the following commands from the base directory of the exercise archive in order to open the circuit template in logisim:

cd count
logisim counter-impl.circ &

In this exercise, there is no specification, you can simulate your circuit in two different ways. In logisim, there is a top level circuit that drives the counter and shows its value on a 7 segment display:

Simulating the counter in logisim

You can advance time by pressing ctrl-T and reset the simulation pressing ctrl-R.

The other possibility is to run logisim from the command line and inspect the waveform by typing make.

Question 1: Open the main circuit and implement a 4-bit modulo counter (thus counting from 0 to 15 and starting over at 0 again) with a synchronous positive reset. Do not use the ready-made counter component of the logisim library (we know it's there), but a register and any arithmetic or logic components you need. You can use the reset provided by the register component or use additional combinatorial logic. Simulate your counter to check if it works correctly.

Question 2: Instead of a modulo counter, we would like to build a counter with saturation arithmetic. This means that it will count up to 15 (shown as F on the 7 segment display) and then keep its value until is is reset.

Question 3: This time, we would like to have an up-and-down counter: It shall start with 0 and count up to 15, then decrement its value until it reaches 0, then start incrementing again.