Synchronous Sequential Logic

Synchronous sequential logic

Memorisation and sequential logic

The combinatorial logical and arithmetic operations presented in the previous chapter all share the following property:

For the same value of the inputs, we always obtain the same output value. In other words, the combinatorial operators have no memory.

We need to keep in mind that these operators have a propagation time that must be respected to be sure that the output result is valid.

How can we use these operators in order to chain several consecutive calculations reliably?

Take as an example the combinatorial function $F$ in the figure below:

Combinatorial bloc and propagation delay

The block has three inputs $E_{0}$ , $E_{1}$ and $E_{2}$ , and a single output $S$ . If we change one of the inputs, we have to wait $t_{p}$ for the result to be valid.

We want to chain several calculations and obtain the following sequence:

$S (0) = F (E_{0} (0), E_{1} (0), E_{2} (0))$
$S (1) = F (E_{0} (1), E_{1} (1), E_{2} (1))$
$S (2) = F (E_{0} (2), E_{1} (2), E_{2} (2))$
…

It must be ensured that the inputs are not modified as long as the output is invalid. However, if the inputs stem from the outside world or from a another computational block, we do not have the guarantee that they remain stable.

Thus, we need to add specific circuit elements in order to capture the values of the inputs and prevent them from changing during the computation, as shown in the following figure:

To simplify the task, capturing and storing the inputs will be done at the same time, synchronously.

Once we are sure that the result is valid (after $t_{p}$ ), we can capture the output result and at the same time present new values on the inputs. The output, thus captured, can in turn be used as input for another computational block.

All of this is summarised in the following figure:

We have the following sequence:

at the time instant $t_{0}$ the inputs are captured (we also say sampled)
at $t_{0} + t_{p}$ the output of the combinatorial block is valid
at $t_{1} > t_{0} + t_{p}$ the output is sampled and new input values captured
And so on …

This logic is called sequential synchronous logic. We have the guarantee that the computations are correct as long as the interval between the sampling instants is greater than the propagation time of the combinatorial block.

In the following, we will see which component is used to sample and memorise the signals and how we synchronise the sampling times.

INF107

Synchronous sequential logic

Memorisation and sequential logic