Immediate Instructions

In this section, we will briefly describe the necessary hardware and its interconnection in order to realise immediate instructions.

Which instructions?

In this section, we will implement I-type instructions:

This includes the following individual instructions:

  • addi (immediate addition)
  • srli (immediate shift right logical)
  • slli (immediate shift left logical)
  • slti (immediate set less than)
  • sltiu (immediate set less than unsigned)
  • xori (immediate bit-wise exclusive or)
  • ori (immediate bit-wise or)
  • andi (immediate bit-wise and)

Note that there is no immediate subtraction. Instead, we can use immediate addition and negate the sign of the immediate value.

What do they do?

Each of these instructions takes one register value and a 32-bit signed constant (obtained by sign extending the 12 bit immediate field from the instruction word), performs some logical or arithmetic computation on them and stores the result in a register. Note that the second operand is replaced by a constant, so for example:

slli x2, x5, 13

will take the value of register x2, shift it left by 13 positions, and store the result in register x5.

What do we need?

Compared to R-type instructions, there is not much to add. All the ALU operations are already implemented. These are the changes that we need:

  1. The decode unit needs to take into account the new opcode and decide if we have an R-type or I-type instruction;
  2. The decode unit needs to produce a 32 bit constant, resulting from the sign-extended 12-bit immediate field in the instruction word;
  3. The wiring of the data path needs to be extended, adding a multiplexer in order to select between a register or immediate value for the second ALU operand.

The data path

The figure below shows the new connections:

Here, we have encapsulated the decode logic in a dedicated hardware module. Besides the known outputs (the ALU operation and register indices), there are two new signals: imm is the 32 bit immediate value, and ALUsrc selects among the two sources for the second operand (register or immediate). The implementation of the decode unit is left as an exercise.